This invention relates to memory devices, particularly to memory devices that can reorganize the data by permuting rows or columns or both. It may be composed of plural memory modules viewed by the processor as a single, nonseparable store. More particularly, it relates to addressing such memory devices such that the processor can selectively modify the address to each module.
The invention provides a memory capable of formatting data before returning it to a processor or writing it back into memory by rearranging rows and columns of data stored in the memory. This is performed faster than a processor can manipulate the same data. The invention can be viewed as altering table structures semantically. It is useful especially in relational database management and uses hardware logic that is independent from the processor so that database management operations can be efficaciously executed off-line, replacing the software that normally performs such operations. It also provides the capability to mask certain data for security reasons, e.g., does not supply data that a user is not authorized to access.
The available techniques for relational database management require several memory accesses to retrieve requested data. The more fields in a record and the more dispersed the requested fields, the more memory read cycles required.
The prior art shows memory arrangements that can modify the data inside the memory per se using logic operations that can be performed without first retrieving the data and then having to restore the result.
U.S. Pat. No. 3,157,778 shows a memory that transfers data from register to register within the memory device and is capable of operating on information within the memory device, e.g., read and increment and return to the same or several registers. Apparently, the memory capacity can be changed by increasing or decreasing the number of registers or the number of storage positions in each registers. The construction is directed to cryogenic techniques.
U.S. Pat. No. 3,247,489 show a memory in which logical operations are performed on data within the memory device without having to retrieve the data. The results can be transferred to external devices, returned to memory, or both. The circuits, disclosed as cryogenic, can simultaneously read, perform a logic operation, and write data by using more than one read and sense line per cell.
U.S. Pat. No. 3,500,341 teaches semiconductor memory stages that perform storage or logical functions. It uses transistor bistable circuits in monolithic arrays and is arranged so that one of the transistors will pass a signal if the other transistor is turned off.
U.S. Pat. No. 3,593,304 teaches a memory that performs logical operations by combining two or more words in a single memory location. Each byte position includes a gate connected to different pairs of adjacent byte lines and produces a signal on one conductor when the signal level on the other exceeds a predetermined value. The byte wires are arranged so the signals add linearly and create carries or propagates via threshold gates, i.e., majority logic gates for each bit position.
U.S. Pat. No. 3,699,534 discloses cellular arithmetic array memories acting as multiprocessors. The invention relates to logic circuits for operating on words while stored in the memory. The circuits can read out, write in, or increment, e.g., an address, during each clock cycle.
U.S. Pat. No. 4,823,257 teaches a processor coupled to several so-called smart memories, i.e., including small scale arithmetic-logic units, which act as coprocessors that prepare data for the processor. By performing such operations--different ALU operations from the host's--and being linked by common intermediate language codes, the number of accesses to a memory is reduced. The results are translated back to intermediate code for the processor. The common intermediate language appears to be the crux of the invention.
For performing simple, low level logical operations on stored data, the prior art is satisfactory. The prior art, however, does not teach the rearrangement of data, using dynamic memory modification under processor control so that a single read (or write) operation that can retrieve (or store) fields of different records from each module even though stored at different addresses.
The invention provides fast retrieval from relational database memories since the addresses can be modified to do in a single memory read that which presently requires several memory reads. It is especially useful in database systems as the systems increase in size and capability.
In accordance with the invention, a memory is made up of several modules addressed as a single unit. Each module has circuits to modify its address selectively. The data read or written at the addressed locations can be selectively rearranged.
Since the registers controlling the address modification logic can be set by the processor in order of magnitude or two faster than a memory cycle, a plurality of selected fields can be accessed in one memory cycle vice several accesses, one for each field at a different address.